1. Field of the Invention
The present invention relates to an associative memory device which has a minimum interface to an external circuit and can be operated at a high speed.
2. Description of the Related Art
A conventional associative memory device of this type has developed, and has been used in port switching of packet data of a LAN (Local Area Network) in the industrial field. However, the conventional associative memory device has developed in a situation where high-speed data communication is not strongly demanded, unlike today. For this reason, the associative memory device is designed to mainly facilitate its peripheral circuit. Therefore, the associative memory device has an arrangement having only an I/O port having a width smaller than a search data width. The prior art described above will be described below.
FIG. 9 is a block diagram showing a conventional device. This conventional associative memory device has: a 16-bit I/O port 51; a 64-bit search data register 52 which receives search data input from this port; a mask register 53 for designating bits to be stored (search target) in the search data register 52 during a search operation; a memory region 50 to be searched; and a hit address register (HHA register) 54 for storing a hit address (HHA) representing a memory word 50a in the memory region 50 which coincides with the search data by the search operation, and comprises an associative memory control circuit 56 including a search control circuit 55 which automatically starts a search operation when data having a certain number of bits (48 bits in this prior art) is input from the I/O port 51 to the search data register 52, i.e., data is input to the search data register 52 three times (when data 1 to 3 in FIG. 9 are input). An address port 57 is prepared to access the registers and the like.
In this prior art, the memory word 50a constituting the memory region 50 has a 64-bit configuration. Of the 64 bits, 48 bits indicate an MAC address serving as a search target, and auxiliary data such as a port number is stored in the remaining 16 bits. This port number Pk represents a port to which a device (terminal) having the MAC address belongs.
A destination MAC address positioned at the beginning of each communication packet data is input to the associative memory device to perform a search operation. With this search operation, the address (hit address (HHA)) of a memory word hit by the search operation is stored in the hit address register 54. A port number Pk stored in the attribute data of the hit memory word 50a is read, and an output port for the packet data is determined by the port number Pk.
Access to an ordinary register such as the search data register 52, the hit address register 54, or the mask register 53 can be performed at a high speed of about 30 to 40 ns. However, with respect to access to the memory region 50 or a search operation, since the memory region 50 serving as the target is designed to have a high density, high-speed access cannot be easily performed, and an access speed of about 80 ns can be achieved at most. As a result, a search processing speed is lowered.
In this case, a general procedure of a search operation will be described below.
A) input of search data (48 bits) PA1 B) search operation PA1 C) hit address (HHA) read PA1 D) incident data of hit memory read
In this procedure, for the operation C) it is necessary to know only the output port number of packet data. However, only the 16-bit data does not have a sufficient arbitrary data width in many cases, and an external RAM is often used. In this case, an external RAM corresponding to the address (HHA) of the hit memory is defined, and data is generally read from the external RAM by using the address (HHA).
The outline of the timing of the operations A) to D) is shown in FIG. 10. In this timing chart, one long rectangle represents 40 ns corresponding to 1 cycle. In this example, the search data processing cycles from T0 to T8 are represented by 8 cycles. Timings T0 and T1, starting from a position below a position where T8 is indicated, represent that the next search data processing cycles continue after the above search data processing cycles.
In this case, 16-bit data is input to the search data register 52 at timings T0, T1, and T2. However, at timing T2, the moment the data is input, a search operation is executed by the search control circuit 55. The search operation accesses the memory region 50, and requires an execution time of 80 ns. Thereafter, at timing T4, a read operation from the hit address register 54 is started, and a read operation from the I/O port 51 is performed at timing T5, 40 ns after.
Next, a read operation of the incident data Pk of the hit word 50a is started at timing T5. The read operation of this data accesses the memory region 50, and requires a time of 80 ns. In this manner, the incident data of the hit word, i.e., the port number Pk, is output from the I/O port 51 at timing T7.
The I/O port 51 is also used as a write port for search data, and search data for processing the next search data cannot be written at timing T7. For this purpose, one dummy cycle is required until the next cycle is started. More specifically, a series of search data processing cycles require 8 cycles (320 ns).
On the other hand, in recent high-speed data communication, the time required to perform the series of search data processing cycles is close to 200 ns, and there is a demand that the search data processing cycles are performed at even higher speed, i.e., within 200 ns. However, as in the above prior art, a conventional associative memory device comprising only one I/O port, having a width smaller than a search data width to facilitate design for a peripheral circuit, cannot provide performance which satisfies the above demand.